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Guillaume Rosaz

3D Integration of Si/SiGe heterostructured nanowires for nanowire transistors

Published on 11 December 2012


Thesis presented December 11, 2012

Abstract:
The goal of this thesis is to build and characterize nanowire based field-effect-transistors. These FET will have either back or wrapping gate using standard CMOS process. Theses transistors will allow us to increase the integration density in back end stages of IC's fabrication and add new functionalities suc as reconfigurable interconnections. The thesis will be done in collaboration between LTM/CNRS and CEA/INAC/SP2M/SiNaPS laboratories using the PTA facilities located in MINATEC.

Keywords:
Nanowire, 3D Integration, Vertical Transistor, Heterostructure, Wrap gate

On-line thesis.