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PhD defense of Thomas Houriez

Electronic circuits at cryogenic temperatures for scalable readout of spin qubits

Published on 6 February 2025
Semiconductor spin qubits are a promising platform for large-scale quantum computing as they benefit from a small footprint and fabrication processes compatible with the established semiconductor industry. While spin qubits are operated at cryogenic temperatures, the electronic circuits ensuring their operation are usually kept at room temperature. Therefore, more than thousands of signals must be conveyed through the cryostat. Moving the control electronics inside the cryostat would improve the system scalability, reducing the connections between room temperature and cryogenic stages to fewer low-frequency cables. This thesis aims to develop cryogenic integrated circuits designed to perform the impedancemetry readout of spin qubits and adapted to large scale readout. Impedancemetry is a readout method similar to the established method of reflectometry, but in which the impedance of the resonator connected to the qubit is measured directly, avoiding the need for complex impedance matching of the resonator. On the other hand, the readout circuits and resonators must be placed in close proximity. First, we present a theoretical study comparing the performances of impedancemetry and reflectometry readout. Impedancemetry demonstrates an improved phase sensitivity since it is limited only by the internal quality factor of the resonator. However, placing the resonator at a higher temperature stage increases its thermal noise, limiting the Signal-to-Noise Ratio (SNR). We perform simulations showing that impedancemetry is compatible with frequency multiplexing, allowing to read several qubits with a single readout chain. Then, we design a circuit in the industrial Fully-Depleted Silicon-On-Insulator (FDSOI) 28nm technology to demonstrate the readout concept. The tests are performed at 4.2K, although the circuit is compatible with an operation at 500mK. During the circuit characterization, an additional discrete SiGe LNA is used. It was also designed during this Ph.D. to be used as the second amplification stage of an impedancemetry or reflectometry readout. At 4.2K, the integrated circuit consumes 590µW for a bandwidth of 500MHz. A digital capacitance is used to emulate the behavior of a qubit and evaluate the sensitivity of the readout chain. The sensitivity is of 35 aF.µV/√Hz at 4.2K, limited by the resonator thermal noise, with an improvement by a factor 3 predicted at 500mK.