Soutenance de thèse
Scalability in fabrication and operation is key to move beyond the NISQ era. So far, superconducting transmon qubits, based on aluminum tunnel Josephson junctions, have demonstrated the most advanced achievements. However, this technology is difficult to use at large scale. Recently, an alternative "gatemon" has appeared using hybrid superconducting/semiconducting (S/Sm) nano-devices as gate-tuned Josephson junctions. Current implementations use nanowires, of which the large-scale fabrication has not yet matured. CMOS Josephson Field-Effect Transistors may be used instead as tunable weak link in a scalable gatemon design, where an ideal device has leads with a large superconducting gap that contact a short channel through high-transparency interfaces. Low contact resistance is achieved in the microelectronics industry with silicides, some of which turn out to be superconducting. The first part of the presentation covers material studies on two such materials: V3Si and PtSi, which are interesting for their high Tc, and mature integration, respectively. The second part covers experimental results on 50nm gate length PtSi transistors, where the transparency of the S/Sm interfaces is modulated by the gate voltage. At low gate voltage, the transport shows no conductance at low energy with well-defined features at the superconducting gap. Increasing the gate voltage reduces the barrier height at the S/Sm interface up to the appearance of a zero bias peak around zero drain voltage which reveals the appearance of an Andreev current. These results suggest the feasibility of fully CMOS-integrated gatemon devices.
Meeting ID: 910 6644 3931
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