Thesis presented December 15, 2010

Abstract:
The use of mechanical stress in the channel of MOSFETs on SOI is mandatory for sub-22 nm technological nodes. Its efficiency depends on the device geometry and design. The impact of different steps of the transistor fabrication process (active area patterning, metal gate formation, Source/Drain (S/D) implantation) on the strain in strained Silicon-On-Insulator (sSOI) materials has been measured by Grazing Incidence X-Ray Diffraction (GIXRD). The electrical performance enhancement of MOSFETs on sSOI has also been estimated with respect to SOI (100% mobility enhancement for long and wide nMOS (L=W=10 μm), 35% saturation drive current (IDsat) enhancement for short and narrow nMOS (L=25 nm, W=77 nm)). Innovative strained structures have then been studied. We demonstrate a 37% (18%) IDsat enhancement for pMOS on SOI (sSOI) with SiGe S/D compared to sSOI with Si S/D, for a 60 nm gate length and a 15 nm film thickness. GIXRD measurements, together with mechanical simulations, enabled the study and optimization of new structures using the stress transfer from an embedded and stressed layer (SiGe or nitride) toward the channel.

Keywords:
strain, stress, mobility, sSOI (strained Silicon-On-Insulator), GIXRD (Grazing Incidence X-Ray Diffraction), MOSFET (Metal Oxide Semiconductor Field Effect Transistor), FDSOI (Fully Depleted Silicon-On-Insulator)

On-line thesis.